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Advanced
CAT25CXXX
Supervisory Circuits with SPI Serial E2PROM, Precision Reset Controller and Watchdog Timer
FEATURES
s 10 MHz SPI Compatible s 1.8 to 6.0 Volt Operation s Hardware and Software Protection s Zero Standby Current s Low Power CMOS Technology s SPI Modes (0,0 &1,1) s Commercial, Industrial and Automotive s Watchdog Timer on CS s 1,000,000 Program/Erase Cycles s 100 Year Data Retention s Self-Timed Write Cycle s 8-Pin DIP/SOIC, 16-Pin SOIC and 14-Pin TSSOP s Page Write Buffer s Block Write Protection
Temperature Ranges
s Active High or Low Reset Outputs
- Protect 1/4, 1/2 or all of E2PROM Array
s Programmable Watchdog Timer s Built-in inadvertent Write Protection
- Precision Power Supply Voltage Monitoring - 5V, 3.3V, 3V and 1.8V Options
- VCC Lock Out
DESCRIPTION
The CAT25CXXX is a single chip solution to three popular functions of EEPROM Memory, precision reset controller and watchdog timer. The EEPROM Memory is a 2K/4K/8K/16K/32K-Bit SPI Serial CMOS E2PROM internally organized as 256x8/512x8/1024x8/2048x8/ 4096x8 bits. Catalyst's advanced CMOS Technology substantially reduces device power requirements. The 2K/4K devices feature a 16-byte page write buffer. The 8K/16K/32K devices feature a 32-byte page write buffer.The device operates via the SPI bus serial interface and is enabled though a Chip Select (CS). In addition to the Chip Select, the clock input (SCK), data in (SI) and data out (SO) are required to access the device. The reset function of the 25CXXX protects the system during brown out and power up/down condtions. During system failure the watchdog timer feature protects the microcontroller with a reset signal. The CAT25CXXX is designed with software and hardware write protection features including Block Lock protection. The device is available in 8-pin DIP, 8-pin SOIC, 16pin SOIC and 14-pin TSSOP packages.
PIN CONFIGURATION
TSSOP Package (U14)
CS SO NC NC NC WP VSS
SOIC Package (S16)
CS SO NC NC NC NC WP VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC RESET/RESET NC NC NC NC SCK SI
SOIC Package (S)
CS SO WP VSS 1 2 3 4 8 7 6 5 VCC RESET/RESET SCK SI
DIP Package (P)
CS SO WP VSS 1 2 3 4 8 7 6 5 VCC RESET/RESET SCK SI
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC RESET/RESET NC NC NC SCK SI
(c) 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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CAT25CXXX
Advanced
PIN FUNCTIONS Pin Name SO SCK WP VCC VSS CS SI RESET/RESET NC Function Serial Data Output Serial Clock Write Protect +1.8V to +6.0V Power Supply Ground Chip Select Serial Data Input Reset I/O No Connect
BLOCK DIAGRAM
SENSE AMPS SHIFT REGISTERS COLUMN DECODERS
WORD ADDRESS BUFFERS
SO SI CS WP SCK
I/O CONTROL SPI CONTROL LOGIC BLOCK PROTECT LOGIC
CONTROL LOGIC
XDEC
E2PROM ARRAY
DATA IN STORAGE HIGH VOLTAGE/ TIMING CONTROL STATUS REGISTER Reset Controller High Precision Watchdog V CC Monitor
25CXXX F02.1
RESET/RESET
RELIABILITY CHARACTERISTICS Symbol NEND(3) TDR(3) VZAP(3) ILTH(3)(4) Parameter Endurance Data Retention ESD Susceptibility Latch-Up Min. 1,000,000 100 2000 100 Max. Units Cycles/Byte Years Volts mA Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17
Power-Up Timing(1)(2) Symbol tPUR tPUW
(1) (2) (3) (4)
Parameter Power-up to Read Operation Power-up to Write Operation
Max. 1 1
Units ms ms
This parameter is tested initially and after a design or process change that affects the parameter. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. This parameter is tested initially and after a design or process change that affects the parameter. Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to VCC +1V.
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CAT25CXXX
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. -55C to +125C Storage Temperature ....................... -65C to +150C Voltage on any Pin with Respect to Ground(1) ............ -2.0V to +VCC +2.0V VCC with Respect to Ground ............... -2.0V to +7.0V Package Power Dissipation Capability (Ta = 25C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300C Output Short Circuit Current(2) ........................ 100 mA D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +6.0V, unless otherwise specified.
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
Limits Symbol ICC1 ICC2 ISB ILI ILO VIL(3) VIH(3) VOL1 VOH1 VOL2 VOH2 Parameter Power Supply Current (Operating Write) Power Supply Current (Operating Read) Power Supply Current (Standby) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage VCC-0.2 VCC - 0.8 0.2 -1 VCC x 0.7 Min. Typ. Max. 5 0.4 0 2 3 VCC x 0.3 VCC + 0.5 0.4 Units mA mA A A A V V V V V V 4.5VVCC<5.5V IOL = 3.0mA IOH = -1.6mA 1.8VVCC<2.7V IOL = 150A IOH = -100A VOUT = 0V to VCC, CS = 0V Test Conditions VCC = 5V @ 5MHz SO=open; CS=Vss VCC = 5.5V FCLK = 5MHz CS = VCC VIN = VSS or VCC
Note: (1) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter.
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Figure 1. Sychronous Data Timing
VIH
tCS
CS
VIL tCSS VIH tCSH
SCK
VIL tSU VIH
tWH tH
tWL
SI
VIL
VALID IN
tV VOH
tHO
tDIS HI-Z
SO
VOL
HI-Z
A.C. CHARACTERISTICS Limits 1.8, 2.5 SYMBOL PARAMETER tSU tH tWH tWL fSCK tLZ tRI(1) tFI(1) tHD tCD tWC tV tHO tDIS tHZ tCS tCSS tCSH Data Setup Time Data Hold Time SCK High Time SCK Low Time Clock Frequency HOLD to Output Low Z Input Rise Time Input Fall Time HOLD Setup Time HOLD HOLD Time Write Cycle Time Output Valid from Clock Low Output HOLD Time Output Disable Time HOLD to Output High Z CS High Time CS Setup Time CS HOLD Time 250 250 250 0 250 100 100 100 100 100 100 10 200 0 75 50 Min. 50 50 200 200 DC 2 50 2 2 40 40 5 80 Max. 4.5V-5.5V Min. 10 20 40 40 DC 10 50 2 2 Max. ns ns ns ns MHz ns s s ns ns ms ns ns ns ns ns ns ns CL = 100pF CL = 50pF Test UNITS Conditions VIH = 2.4V CL = 100pF VOL = 0.8V VOH = 2.0v
NOTE: (1) This parameter is tested initially and after a design or process change that affects the parameter.
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Advanced
CAT25CXXX
RESET/RESET RESET I/O RESET: RESET These are open drain pins and can be used as reset trigger inputs. By forcing a reset condition on the pins the device will initiate and maintain a reset condition. RESET pin must be connected through a pull-down and RESET pin must be connected through a pull-up device. CS: CS Chip Select CS is the Chip select pin. CS low enables the CAT25CXXX and CS high disables the CAT25CXXX. CS high takes the SO output pin to high impedance and forces the devices into a Standby Mode (unless an internal write operation is underway) The CAT25CXXX draws ZERO current in the Standby mode. A high to low transition on CS is required prior to any sequence being initiated. A low to high transition on CS after a valid write sequence is what initiates an internal write cycle.
FUNCTIONAL DESCRIPTION
The CAT25CXXX supports the SPI bus data transmission protocol. The synchronous Serial Peripheral Interface (SPI) helps the CAT25CXXX to interface directly with many of today's popular microcontrollers. The CAT25CXXX contains an 8-bit instruction register. (The instruction set and the operation codes are detailed in the instruction set table) After the device is selected with CS going low, the first byte will be received. The part is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The first byte contains one of the six op-codes that define the operation to be performed.
PIN DESCRIPTION
SI: Serial Input SI is the serial data input pin. This pin is used to input all opcodes, byte addresses, and data to be written to the 25CXXX. Input data is latched on the rising edge of the serial clock. SO: Serial Output SO is the serial data output pin. This pin is used to transfer data out of the 25CXXX. During a read cycle, data is shifted out on the falling edge of the serial clock. SCK: Serial Clock SCK is the serial clock pin. This pin is used to synchronize the communication between the microcontroller and the 25CXXX. Opcodes, byte addresses, or data present on the SI pin are latched on the rising edge of the SCK. Data on the SO pin is updated on the falling edge of the SCK.
WP Write Protect WP: WP is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When WP is tied low and the WPEN bit in the status register is set to "1", all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit is set to 0.
INSTRUCTION SET Instruction WREN WRDI RDSR WRSR READ WRITE Opcode 0000 0110 0000 0100 0000 0101 0000 0001 0000 X011(1) 0000 X010(1) Operation Enable Write Operations Disable Write Operations Read Status Register Write Status Register Read Data from Memory Write Data to Memory
Note: (1) X=O for 25C02X/08X/16X/32X. X=A8 for 25C04X
STATUS REGISTER 7 WPEN 6 X 5 WD1 4 WD0 3 BP1 2 BP0 1 WEL 0 RDY
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Status Register The Status Register indicates the status of the device. The RDY (Ready) bit indicates whether the CAT25CXXX is busy with a write operation. When set to 1 a write cycle is in progress and when set to 0 the device indicates it is ready. This bit is read only.The WEL (Write Enable) bit indicates the status of the write enable latch . When set to 1, the device is in a Write Enable state and when set to 0 the device is in a Write Disable state. The WEL bit can only be set by the WREN instruction and can be reset by the WRDI instruction. The BPO and BP1 (Block Protect) bits indicate which blocks are currently protected. These bits are set by the user issuing the WRSR instruction. The user is allowedto protect quarter of the memory, half of the memory or the entire memory by setting these bits. Once protectedthe user may only read from the protected portion of the array. These bits are non-volatile. The WPEN (Write Protect Enable) is an enable bit for the WP pin. The WP pin and WPEN bit in the status register control the programmable hardware write protect feature. Hardware write protection is enabled when WP is low and WPEN bit is set to high. The user cannot write to the status register, (including the block protect bits and the WPEN bit) and the block protected sections in the memory array when the chip is hardware write protected. Only the sections of the memory array that are not block protected can be written. Hardware write protection is disabled when either WP pin is high or the WPEN bit is zero. The watchdog timer bits, WD0 and WD1, select the watchdog time-out period. These nonvolatile bits are programmed with the WRSR instruction.
BLOCK PROTECTION BITS Status Register Bits BP1 BPO 0 0 0 1 Array Address Protected None 25C02X: C0-FF 25C04X: 180-1FF 25C08X: 0300-03FF 25C16X: 0600-07FF 25C32X: 0C00-0FFF 25C02X: 80-FF 25C04X: 100-1FF 25C08X: 0200-03FF 25C16X: 0400-07FF 25C32X: 0800-0FFF 25C02X: 00-FF 25C04X: 000-1FF 25C08X: 0000-03FF 25C16X: 0000-07FF 25C32X: 0000-0FFF Protection No Protection Quarter Array Protection
1
0
Half Array Protection
1
1
Full Array Protection
WATCHDOG TIMER BITS WD1 0 0 1 1 WD0 0 1 0 1 Watchdog Timer Time-Out (Typical) 1.4 Seconds 600 Milliseconds 200 Milliseconds Disabled
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CAT25CXXX
DEVICE OPERATION FOR THE MEMORY FUNCTION Write Enable and Disable The CAT25CXXX contains a write enable latch. This latch must be set before any write operation. The device powers up in a write disable state when Vcc is applied. WREN instruction will enable writes (set the latch) to the device. WRDI instruction will disable writes (reset the latch) to the device. Disabling writes will protect the device against inadvertent writes. READ Sequence The part is selected by pulling CS low. The 8-bit read instruction is transmitted to the CAT25CXXX, followed by the 16-bit address for 25C08X/16X/32X (only 10-bit addresses are used for 25C08X, 11-bit addresses are used for 25C16X, and 12-bit addresses are used for 25C32X. The rest of the bits are don't care bits) and 8bit address for 25C02X/04X (for the 25C04X, bit 3 of the read data instruction contains address A8). After the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address WRITE PROTECT ENABLE OPERATION WPEN 0 0 1 1 X X WP X X Low Low High High WEL 0 1 0 1 0 1
after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to 0000H allowing the read cycle to be continued indefinitely. The read operation is terminated by pulling the CS high. To read the status register, RDSR instruction should be sent. The contents of the status register are shifted out on the SO line. The status register may be read at any time even during a write cycle. Read sequece is illustrated in Figure 4. Reading status register is illustrated in Figure 5. WRITE Sequence The CAT25CXXX powers up in a Write Disable state. Prior to any write instructions, the WREN instruction must be sent to CAT25CXXX. The device goes into w rite enable state by pulling the CS low and then clocking the WREN instruction into CAT25CXXX. The CS must be brought high after the WREN instruction to enable writes to the device. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set. Also, for a successful write operation the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block protection level.
Protected Blocks Protected Protected Protected Protected Protected Protected
Unprotected Blocks Protected Writable Protected Writable Protected Writable
Status Register Protected Writable Protected Protected Protected Writable
Figure 2. WREN Instruction Timing
SK
CS
SI
0
0
0
0
0
1
1
0
SO
HIGH-Z
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Byte Write Once the device is in a Write Enable state, the user may proceed with a write sequence by setting the CS low, issuing a write instruction via the SI line, followed by the 16-bit address for 25C08X/16X/32X (only 10-bit addresses are used for 25C08X, 11-bit addresses are used for 25C16X, and 12-bit addresses are used for 25C32X. The rest of the bits are don't care bits) and 8bit address for 25C02X/04X (for the 25C04X, bit 3 of the read data instruction contains address A8). Programming will start after the CS is brought high. The low to high transition of the CS pin must occur during the SCK low time, immediately after clocking the least significant bit of the data. Figure 6 illustrates byte write sequence. During an internal write cycle, all commands will be ignored except the RDSR (Read Status Register) instruction. The Status Register can be read to determine if the write cycle is still in progress. If Bit 0 of the Status Register is set at 1, write cycle is in progress. If Bit 0 is set at 0, the device is ready for the next instruction. Figure 3. WRDI Instruction Timing
Page Write The CAT25CXXX features page write capability. After the initial byte, the host may continue to write up to 16 bytes of data to the CAT25C02X/04X and 32 bytes of data for 25C08X/16X/32X. After each byte of data received, lower order address bits are internally incremented by one; the high order bits of address will remain constant.The only restriction is that the X (X=16 for 25C02X/04X and X=32 for 25C08X/16X/32X) bytes must reside on the same page. If the address counter reaches the end of the page and clock continues, the counter will "roll over" to the first address of the page and overwrite any data that may have been written. The CAT25CXXX is automatically returned to the write disable state at the completion of the write cycle. Figure 8 illustrates the page write sequence. To write to the status register, the WRSR instruction should be sent. Only Bit 2, Bit 3 and Bit 7 of the status register can be written using the WRSR instruction. Figure 7 illustrates the sequence of writing to status register.
SK
CS
SI
0
0
0
0
0
1
0
0
SO
HIGH-Z
25C128 F05
Figure 4. Read Instruction Timing
RESET 0 SK 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30
CS
SI
0
0
0
0
0
0
1
1
BYTE ADDRESS*
SO
7
6
5
4
3
2
1
0
*Please check the instruction set table for address
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CAT25CXXX
Figure 5. RDSR Timing
CS
0 SCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SI DATA OUT 7 MSB
25C128 F09
SO
HIGH IMPEDANCE
6
5
4
3
2
1
0
Figure 6. Write Instruction Timing
0 SK
1
2
3
4
5
6
7
8
21
22
23
24
25
26
27
28
29
30
31
CS
SI
0
0
0
0
0
0
1
0
ADDRESS
D7 D6 D5 D4 D3 D2 D1 D0
SO
Figure 7. WRSR Timing
CS 0 SCK DATA IN 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
INSTRUCTION SI
SO
25C128 F08
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DEVICE OPERATION FOR THE SUPERVISORY CIRCUIT
Reset Controller Description
The CAT25CXXX provides a precision RESET controller that ensures correct system operation during brownout and power-up/down conditions. It is configured with open drain RESET outputs. During power-up, the RESET outputs remain active until VCC reaches the VTH threshold and will continue driving the outputs for approximately 200ms (tPURST) after reaching VTH. After the tPURST timeout interval, the device will cease to drive reset outputs. At this point the reset outputs will be pulled up or down by their respective pull up/pull down devices. During power-down, the RESET outputs will begin driving active when VCC falls below VTH. The RESET outputs will be valid so long as VCC is >1.0V (VRVALID). The RESET pins are I/Os; therefore, the CAT25CXXX can act as a signal conditioning circuit for an externally applied reset. The inputs are level triggered; that is, the RESET input in the 25CXXX will initiate a reset timeout after detecting a high and the RESET input in the 25CXXX will initiate a reset timeout after detecting a low.
time out period (the time out period is defined by the watchdog timer bits WD0 an d WD1) for lack of activity. 25CXXX is designed with the Watchdog Timer feature on the CS input. For the 25CXXX, if the microcontroller does not toggle the CS pin within the time out period the Watchdog Timer times out. This will generate a reset condition on reset outputs. The Watchdog Timer is cleared by any transition on CS. As long as the reset signal is asserted, the Watchdog Timer will not count and will stay cleared. Reset Threshold Voltage From the factory the 25CXXX is offered in six different variations of reset threshold voltages. They are 4.504.75V, 4.25-4.50V, 3.00-3.15V, 2.85-3.00V, 2.55-2.70V and 1.7-1.8V. To provide added flexibility to design engineers using this product, the 25CXXX is designed with an additional feature of programming the reset threshold voltage. This allows the user to change the existing reset threshold voltage to one of the other five reset threshold voltages. Once the reset threshold voltage is selected it will not change even after cycling the power, unless the user uses the programmer to change the reset threshold voltage. However, the programming function is available only through third party programmer manufacturers. Please call Catalyst for a list of programmer manufacturers who support this function.
Watchdog Timer
The Watchdog Timer provides an independent protection for microcontrollers. During a system failure, the CAT25CXXX will respond with a reset signal after a Figure 8. Page Write Instruction Timing
0 SK
1
2
3
4
5
6
7
8
21
22
23 24-31
32-39
CS
SI
0
0
0
0
0
0
1
0
ADDRESS
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte N
SO
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CAT25CXXX
RESET CIRCUIT CHARACTERISTICS
Symbol
tGLITCH VRT VOLRS VOHRS
Parameter
Glitch Reject Pulse Width Reset Threshold Hystersis Reset Output Low Voltage (IOLRS=1mA) Reset Output High Voltage Reset Threshold (Vcc=5V) (25CXXX-45) Reset Threshold (Vcc=5V) (25CXXX-42)
Min.
Max.
100
Units
ns mV
15 0.4 Vcc-0.75 4.50 4.25 3.00 2.85 2.55 1.70 130 4.75 4.50
V V
V 3.15 3.00 2.70 1.80 270 5 1 ms s V
VTH
Reset Threshold (Vcc=3.3V) (25CXXX-30) Reset Threshold (Vcc=3.3V) (25CXXX-28) Reset Threshold (Vcc=3V) (25CXXX-25) Reset Threshold (Vcc=1.8V) (25CXXX-17)
tPURST tRPD
Power-Up Reset Timeout VTH to RESET Output Delay RESET Output Valid
VRVALID
Figure 9. RESET Output Timing
t
GLITCH
VTH VRVALID VCC t PURST t RPD t PURST
RESET
t RPD
RESET
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Advanced
DESIGN CONSIDERATIONS The CAT25CXXX powers up in a write disable state and in a low power standby mode. A WREN instruction must be issued to perform any writes to the device after power up. Also,on power up CS should be brought low to enter a ready state and receive an instruction. After a successful byte/page write or status register write the CAT25CXXX goes into a write disable mode. CS must be set high after the proper number of clock cycles to start an internal write cycle. Access to the array during an internal write cycle is ignored and programming is continued. On power up,SO is in a high impedance. If ORDERING INFORMATION Prefix CAT Device # 25C16
1
an invalid op code is received, no data will be shifted into the CAT25CXXX, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. The VCC sense provides write protection when VCC falls below the reset threshold value (VTH). The VCC lock out inhibits writes to the serial EEPROM whenever VCC falls below (power down) VTH or until VCC reaches the reset threshold (power up) VTH.
Suffix S I Temperature Range Blank = Commercial (0C to +70C) I = Industrial (-40C to +85C) A = Automotive (-40 to +105C)* -30 TE13
Optional Company ID
Product Number 25C32: 32K 25C16:16K 25C08: 8K 25C04: 4K 25C02: 2K
RESET
1. RESET 2. RESET
Tape & Reel TE13: 2000/Reel
Package P = PDIP S = 8-pin SOIC S16 = 16-pin SOIC U14 = 14-pin TSSOP * -40C to +125C is available upon request
Reset Threshold Voltage 45: 4.5-4.75V 42: 4.25-4.5V 30: 3.0-3.15V 28: 2.85-3.0V 25: 2.55-2.7V 17: 1.7-1.8V
Notes: (1) The device used in the above example is a 25C161SI-30TE13 (RESET, SOIC, Industrial Temperature, 3.0-3.15 Reset Threshold Voltage, Tape & Reel)
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